Lan Hương

High-performance Transimpedance Amplifier (TIA) for DAC current-to-voltage conversion with low noise and high linearity.

RTL design of a Viterbi Decoder for (2,1,2) convolutional code (K=3, R=1/2) in Verilog. Includes extract bit , branch metric, add-compare-select, path metric memory, and traceback modules with testbench.

Two-stage folded cascode CMOS operational amplifier designed in 45nm GPDK045 using Cadence Virtuoso. 120 MHz GBW, 20 V/µs slew rate, 144 µW power.

No description.