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C++

0dMIPS

[WIP] in-order 5(+1)-stages pipeline MIPS64r6el SoC implementation with peripheral components, simulated with verilator

C++Emergingmips64systemverilogverilator
GitHubWebsite
Stars
8
Forks
2
Contributors
1
Last push
16h ago

Recent commits

Latest commits.

  • feat: add branch predictor
    6bdabdbEritque arcus16h ago
  • perf: better timing
    1603bf5Eritque arcus2d ago
  • perf: better timing
    144d571Eritque arcus2d ago
  • fix: fix github test action trigger
    87a0eaferitque0arcus10d ago
  • fix: fix cache_L1 test random addr alignment
    b3351e2eritque0arcus10d ago
fix: fix cacheL1 and add cacheL1 tests
4a9d8c6eritque0arcus10d ago
  • better readme for board
    9bc7f73Eritque arcus12d ago
  • chore: better readme
    f7c3ca5Eritque arcus12d ago

    • Top contributors

    Builders behind this project.

    Nambers
    143 commits