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float_synth
What if we synthesize IEEE.float_pkg?
VHDL
Emerging
abc
floating-point
ghdl
synthesis
GitHub
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11
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1
Last push
2mo ago
Recent commits
Latest commits.
doc: update results
10e4a09
NikLeberg
2mo ago
dev: workaround nvc verilog bug
5eb8b57
NikLeberg
2mo ago
src/gen: add generated fmul16 variants
9a9e82a
NikLeberg
2mo ago
dev: report per entity usage
f0d626f
NikLeberg
2mo ago
dev: add quartus build script
8ccbe57
NikLeberg
3mo ago
src: switch base generation to verilog
5d2b7d4
NikLeberg
3mo ago
src/gen: update generated files
810fc56
NikLeberg
3mo ago
src: reduce depth of adder to 7
03b5d37
NikLeberg
3mo ago
Top contributors
Builders behind this project.
NikLeberg
41 commits
