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nvc
VHDL compiler and simulator
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8
Last push
1mo ago
Recent commits
Latest commits.
Handle various combination of real and vector operands
2deb4f1
Nick Gasson
2mo ago
Make JIT floating point comparison consistently ordered
15b65b4
Nick Gasson
2mo ago
Fix crash with empty Verilog parameter assignment
ccef2b6
Nick Gasson
2mo ago
Fix invalid cast error when Verilog repeat statement has real count
bf7169b
Nick Gasson
2mo ago
Parse period timing check (#1507)
05718de
Ondrej Ille
2mo ago
Fix lowering of Verilog repeat with non-constant count
88306c0
Nick Gasson
2mo ago
Fix invalid cast in Verilog repeat statement
8586023
Nick Gasson
2mo ago
Add Verilog casez support
8fe89e6
Nick Gasson
2mo ago
Top contributors
Builders behind this project.
nickg
7.1K commits
hiyuh
90 commits
Blebowski
82 commits
mitchsm
72 commits
Forty-Bot
53 commits
NikLeberg
35 commits
sean-anderson-seco
19 commits
bpadalino
13 commits