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SystemVerilog

advent-of-fpga

Advent of FPGA — A Jane Street Challenge

SystemVerilogEmergingaocchdlpython
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1
Last push
5mo ago

Recent commits

Latest commits.

  • VHDL version - forgot that Vivado does not like SystemVerilog except for simulation sources
    b5b83eePaolo Cancedda5mo ago
  • Let's use INPUT_FILENAME
    2389623Paolo Cancedda5mo ago
  • .gitignore for c
    d8a41faPaolo Cancedda5mo ago
  • Simplify Makefile
    34da941Paolo Cancedda5mo ago
  • Include license details in README
    2d86647Paolo Cancedda5mo ago
Update README with improved phrasing and formatting
408b3d1Paolo Cancedda5mo ago
  • Rename 'Solution' to 'A Solution' in README
    c2330d5Paolo Cancedda5mo ago
  • Clarify input file usage and update section titles
    dfe300fPaolo Cancedda5mo ago

    • Top contributors

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    Pac72
    22 commits