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Verilog

gf180mcu_ocd_ip_sram

3.3V SRAM macros for GF180MCU, based on the original 5V SRAM macros.

VerilogEmerging

Stars

15

Forks

4

Contributors

3

Last push

9h ago

Recent commits

Latest commits.

Added a 64-byte memory block to the existing 1024, 512, and 256 byte blocks. The reason for
2d78931R. Timothy Edwards9h ago
Merge pull request #1 from robtaylor/recharacterise-specify-block-from-csv
145d144R. Timothy Edwards29d ago
Merge branch 'main' into recharacterise-specify-block-from-csv
80a8528R. Timothy Edwards29d ago
Merge pull request #2 from mole99/leo/blackbox
eac822eR. Timothy Edwards1mo ago
Add blackbox views
ae8fa98

Leo Moser

1mo ago

Modified the LEF view generation script to change the "hide" setback from 6um to 3um.

5144de6R. Timothy Edwards1mo ago

Recharacterise specify-block timing in sram1024x8m8wm1.v from spec CSVs

8cbbb37Rob Taylor1mo ago

Updated libraries after feedback from GF via wafer.space; a rule in

2c2a601R. Timothy Edwards6mo ago

Top contributors

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RTimothyEdwards