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Idris

verilog-model

DepTyCheck model for semantically correct SystemVerilog descriptions

IdrisEmerging

Stars

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Forks

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Contributors

4

Last push

3mo ago

Recent commits

Latest commits.

[ ci ] Print errors stats comparison
eea0600L3odr0id3mo ago
[ new ] VHDL connections model
3d43b99L3odr0id3mo ago
[ new ] basic VHDL support
457dde2L3odr0id5mo ago
[ lint ] Add linter to the CI
11e21c4Denis Buzdalov5mo ago
[ fix ] Pass cache key to publish-container job
97452aaL3odr0id7mo ago

[ ci ] Comment out tests & report issues occurrence

b814034L3odr0id7mo ago

[ fix ] Unpacked array conns type

15cca41L3odr0id8mo ago

[ refactor ] Rename basic types

71e1f14L3odr0id9mo ago

Top contributors

Builders behind this project.