Loreon
Labs
Platform
Docs
Home
Ecosystems
Verilog
zipcpu
A small, light weight, RISC CPU soft core
Verilog
Building
cpu
cross-compiler
fpga
risc-cpu
GitHub
Stars
1.6K
Forks
180
Contributors
8
Last push
6mo ago
Recent commits
Latest commits.
Merge branch 'master' of github.com:ZipCPU/zipcpu
42606d2
ZipCPU
10mo ago
Marked PIPEFETCH as DEPRECATED (again)
ecc8a34
ZipCPU
10mo ago
FIX: Make clean target had incorrect clean syntax
9a20c17
ZipCPU
11mo ago
FIX: (at least should fix ...) vversion permission issue
d2610c4
ZipCPU
11mo ago
Merge pull request #41 from JacyCui/fix
5dd51f5
Dan Gisselquist
11mo ago
Remove duplicated assignment
45996e8
JacyCui
11mo ago
FIX: Patch issues, removed zip-ops.md from GCC patch
8f12b10
ZipCPU
17mo ago
FIX: Toolchain bugs
91d8d9d
ZipCPU
17mo ago
Top contributors
Builders behind this project.
ZipCPU
767 commits
foobar2016
34 commits
Sya0
17 commits
Olf0
3 commits
Sukru-Uzun
2 commits
bman12three4
1 commits
JacyCui
1 commits
hasheddan
1 commits
