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uvm_code_gen
Simple template-based UVM code generator
SystemVerilog
Emerging
systemverilog
uvm
GitHub
Stars
30
Forks
5
Contributors
2
Last push
2mo ago
Recent commits
Latest commits.
doc: add docstring
b891744
antoinemadec
2mo ago
feat(test): add warning when no simulator was found
b135bd8
antoinemadec
42mo ago
feat: add support for VCS
a08d199
antoinemadec
42mo ago
refactor(naming): rename "rst" to "rstn"
366d103
antoinemadec
43mo ago
Merge pull request #1 from vmorillon/main
2f392e5
Antoine
44mo ago
support legacy type hinting
26d1bfd
vmorillon
44mo ago
feat: use --format to format generated SV files
e8b49f5
antoinemadec
44mo ago
refactor: change SB port name to _export instead of _to_scoreboard
7700b94
antoinemadec
44mo ago
Top contributors
Builders behind this project.
antoinemadec
36 commits
vmorillon
1 commits
