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SystemVerilog

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilogEmerging

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Contributors

8

Last push

1mo ago

Recent commits

Latest commits.

Merge branch 'chipsalliance:master' into master
5421df6Cary R.1mo ago
Merge pull request #8520 from chipsalliance/dependabot/submodules/third_party/tools/slang-20cce3a
1c456cegithub-actions[bot]1mo ago
Merge pull request #8518 from chipsalliance/dependabot/submodules/third_party/tools/yosys-e87a9bd
bf7319bgithub-actions[bot]1mo ago
Merge pull request #8517 from chipsalliance/dependabot/submodules/third_party/tools/circt-verilog-bc8f154
512dc1egithub-actions[bot]1mo ago
Merge pull request #8519 from chipsalliance/dependabot/submodules/third_party/tools/icarus-73ae5bd
d323a46

github-actions[bot]

1mo ago

Merge pull request #8516 from chipsalliance/dependabot/submodules/third_party/tools/verilator-4e853d8

2947320github-actions[bot]1mo ago

build(deps): bump third_party/tools/slang from `861ec67` to `20cce3a`

a3a2ad4dependabot[bot]1mo ago

build(deps): bump third_party/tools/icarus from `a8eda65` to `73ae5bd`

0d19925dependabot[bot]1mo ago

Top contributors

Builders behind this project.

dependabot[bot]

github-actions[bot]

dependabot-preview[bot]