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common_cells

Common SystemVerilog components

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8

Last push

16mo ago

Recent commits

Latest commits.

Release v1.38.0
9afda9aNils Wistoff16mo ago
rr_arb_tree: Remove redundant param implication from lock asserts (#253)
2fdef04Michael Platzer17mo ago
Bender.yml: Don't import deprecated SRAM with Verilator (#249)
f36828fMoritzScherer19mo ago
fall_through_register: Fix module description (#244)
e66a131Matteo Perotti19mo ago
delta_counter: Fix inverted reset (#242)
554ebbcOlof Kindgren21mo ago

assertions: Keep helper macros defined (#240)

94d285bMichael Platzer21mo ago

addr_decode: Guard unsynthesizable `$isunknown` (#239)

7d90f2eMichael Platzer21mo ago

README: Update documentation of assertion macros (#237)

ef7d003Michael Platzer21mo ago

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michael-platzer