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luna-usb-serial-acm
gregdavill/luna-usb-serial-acm
Verilog
Emerging
GitHub
Stars
3
Forks
1
Contributors
1
Last push
13d ago
Recent commits
Latest commits.
fix: fix readme typo
ef1d7dc
Greg Davill
5mo ago
feat: Add cdc fifos to support dual clock domains
ebb995c
Greg Davill
33mo ago
feat: add building instructions to readme
7cd2fde
Greg Davill
5mo ago
fix: add .o elements to i/o ports
f61acb4
Greg Davill
5mo ago
fix: update nmigen to amaranth
eda5e47
Greg Davill
5mo ago
Add 40ms to PHY reset controller
52f6427
Greg Davill
55mo ago
Update vdir
0d02306
Greg Davill
55mo ago
Initial commit
795296b
Greg Davill
55mo ago
Top contributors
Builders behind this project.
gregdavill
8 commits
