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frost
A simple RISC-V CPU implemented in Verilog
Assembly
Emerging
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1
Last push
60mo ago
Recent commits
Latest commits.
Rename wire with more appropriate name.
2bcfd73
null-a
60mo ago
Add timing diagram for memory reads.
a112d0c
null-a
61mo ago
Move clearing of LSB before mux.
f36ba4e
null-a
60mo ago
Fix bug: JALR ought to clear the LSB of the target PC.
8156f03
null-a
60mo ago
Mention M-mode/interrupts in the readme.
f23aba3
null-a
61mo ago
Use same stdlib everywhere.
a3d3c6a
null-a
61mo ago
Revert to simpler blinky implementation.
8407410
null-a
61mo ago
Initial attempt at a threads demo.
e90d5f5
null-a
61mo ago
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113 commits
