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C

nvc

VHDL compiler and simulator

CEmerging

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8

Last push

18d ago

Recent commits

Latest commits.

Handle subtype in instantiated package in lower_get_type_bounds
5331860Nick Gasson18d ago
Specify architectures on command line with entity(arch)
11a6369Nick Gasson18d ago
Minor documentation fixes (#1557)
eaf34c6Oscar Gustafsson18d ago
Handle out-of-range select on LHS of local variable assignment
e930f55Nick Gasson20d ago
Implement $itor system function
97397e7Nick Gasson24d ago

Lower Verilog min:typ:max expressions

ad92ae6Nick Gasson24d ago

Constant fold replication count in Verilog concatenation (#1551)

9ee61a5Matthias Alles24d ago

cLowering for System Verilog $bits

1e91536Nick Gasson24d ago

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sean-anderson-seco