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Verilog

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

VerilogEmerging
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8
Last push
3mo ago

Recent commits

Latest commits.

  • ram: Create initial README.md
    4aab880Austin Rovinski3mo ago
  • Merge pull request #9836 from osamahammad21/dbSta-chip-no-block
    e034522Osama Hammad3mo ago
  • Merge pull request #9815 from rohithsiddi/odb-test-destroy-missing-types
    135c25dMatt Liberty3mo ago
  • Merge pull request #9838 from gadfort/pdn-min-area
    e8b49c7Peter3mo ago
  • pdn: condense delta
    a849bd2Peter Gadfort3mo ago
pdn: shapes that ultimimately do not work
d68ff5cPeter Gadfort3mo ago
  • Merge pull request #9845 from eder-matheus/tap_fix
    1bec6caEder Monteiro3mo ago
  • Merge pull request #9841 from The-OpenROAD-Project-staging/dpl_fill_insertion
    a1ac31aEder Monteiro3mo ago

    • Top contributors

    Builders behind this project.

    maliberty
    8.4K commits
    eder-matheus
    5.6K commits
    jjcherry56
    3.2K commits
    gadfort
    3K commits
    osamahammad21
    2K commits
    AcKoucher
    1.2K commits
    gudeh
    973 commits
    jhkim-pii
    758 commits