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nvc
VHDL compiler and simulator
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1
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Contributors
8
Last push
30mo ago
Recent commits
Latest commits.
Implement VHDL-2019 shared variables on entity interface (LCS2016-47)
e004198
Nick Gasson
38mo ago
Refactoring to allow ports with variable class
3267103
Nick Gasson
38mo ago
Enable "function knows vector size" for unconstrained records
9d95fc6
Nick Gasson
38mo ago
Allow "function knows vector size" in declarations and signal assignments
918f2d0
Nick Gasson
38mo ago
Add some basic support for LCS2016-72b "function knows vector size"
2bc4d69
Nick Gasson
38mo ago
Optimise lookup_item
736de11
Nick Gasson
38mo ago
Store Verilog numbers in AST
5190fa9
Nick Gasson
38mo ago
Cover conditional return test (#692)
9296e79
Blebowski
38mo ago
Top contributors
Builders behind this project.
nickg
5.1K commits
hiyuh
90 commits
mitchsm
72 commits
Blebowski
24 commits
bpadalino
7 commits
peteut
6 commits
kraigher
6 commits
nabilmerk
4 commits
