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SystemVerilog

SDNet_proj

Simple Vivado project to test SDNet

SystemVerilogEmerging

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1

Last push

76mo ago

Recent commits

Latest commits.

Adding lnic_v2_egress.p4. Appears to be working :-)
4fdaf8aStephen Ibanez76mo ago
Adding lnic_v2_ingress.p4 and test files. Looks like it is working.
19521aeStephen Ibanez76mo ago
Adding traffic files
d623e67Stephen Ibanez76mo ago
Updated datapath width to 512 bits
22cd755Stephen Ibanez76mo ago
Updated .gitignore
fc5f61bStephen Ibanez76mo ago

Removed unused sw/ directory

b3f671aStephen Ibanez76mo ago

Updated README with description of SDNet issues

caca7a4Stephen Ibanez76mo ago

Minor updates and gitignore file

a1e842eStephen Ibanez76mo ago

Top contributors

Builders behind this project.