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Verilog

tt09-jtag-example-v2-stevej

stevej/tt09-jtag-example-v2-stevej

VerilogEmerging
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1
Last push
9mo ago

Recent commits

Latest commits.

  • don't start at 0, make enough room for states
    86a5fcdSteve Jenson9mo ago
  • fpga workflow isn't important, I guess
    697c4b9Steve Jenson20mo ago
  • SystemVerilog and moving to logic
    ffb1bdeSteve Jenson20mo ago
  • moving to always_ff
    f52449fSteve Jenson20mo ago
  • get rid of stale comments
    7d08e29Steve Jenson20mo ago
run fpga workflow on each push
5d0d22eSteve Jenson20mo ago
  • fewer flops for FSM encoding
    20d6412Steve Jenson20mo ago
  • X hunting in tms reset logic
    d64bfa1Steve Jenson20mo ago

    • Top contributors

    Builders behind this project.

    stevej
    69 commits